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data sheet low skew, 1:18 crystal-to-lvcmos/lvttl fanout buffer 83918 83918 rev b 3/25/15 1 ?2015 integrated device technology, inc. general description the 83918 is a low skew, 1:18 crystal-to- lvcmos/lvttl fanout buffer. the 83918 has selectable lvcmos/lvttl clock or crystal inputs. the low impedance lvcmos /lvttl outputs are designed to drive 50 ? series or parallel terminated transmission lines. the 83918 is characterized at full 3.3v, full 2.5v and mixed 3.3v/2.5v, 3.3v/1.8v, and 2.5v/1.8v output operating supply modes. guaranteed output and part-to-part skew characteristics make the 83918 ideal for those clock distribution applications demanding well defined performance and repeatability. features ? eighteen lvcmos/lvttl output ? selectable crystal oscillator interface or lvcmos_clk ? maximum output frequency: 200mhz ? crystal input frequency range: 10mhz to 40mhz ? rms phase jitter using a 25mhz crystal (1khz ? 1mhz): 0.449ps (typical) @ 3.3v/3.3v ? output skew: 75ps (maximum) @ 3.3v/3.3v ? operating supply modes: core/output 3.3v/3.3v 3.3v/2.5v 3.3v/1.8v 2.5v/2.5v 2.5v/1.8v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package osc 0 1 18 q0:q17 pulldown pulldown clk_sel lvcmos_clk xtal_in xtal_out 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 q6 q7 q8 v ddo q9 q10 q11 gnd gnd gnd lvcmos_clk clk_sel xtal_in xtal_out v dd v ddo gnd q5 q4 q3 v ddo q2 q1 q0 q17 q16 q14 q15 gnd q13 q12 v ddo pin assignment 83918 32 lead lqfp 7mm x 7mm x 1.4mm package body y package top view block diagram
rev b 3/25/15 2 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet table 1. pin descriptions note: pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2, 12, 17, 25 gnd power power supply ground. 3 lvcmos_clk input pulldown single-ended clock i nput. lvcmos/lvttl interface levels. 4 clk_sel input pulldown clock select pin. when high, se lects lvcmos_clk. when low, selects crystal inputs. lvcm os/lvttl interface levels. 5, 6 xtal_in, xtal_out input crystal oscillator interface. xtal_i n is the input, xtal_out is the output. 7v dd power positive supply pin. 8, 16, 21, 29 v ddo power output supply pins. 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 q17, q16, q15, q14, q13, q12, q11, q10, q9, q8, q7, q6, q5, q4, q3, q2,q1, q0 output single-ended clock outputs. lv cmos/lvttl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf c pd power dissipation capacitance (per output) v ddo = 3.465v 9 pf v ddo = 2.625v 8 pf v ddo = 2v 8 pf r pulldown input pulldown resistor 51 k ? r out output impedance v ddo = 3.465v 18 19 20 ? v ddo = 2.625v 20 22 24 ? v ddo = 2v 25 29 34 ?
low skew, 1:18 crystal-to-lvcmos/lvttl fanout buffer 3 rev b 3/25/15 83918 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = v ddo = 3.3v5%, t a = -40c to 85c table 3b. power supply dc characteristics, v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c table 3c. power supply dc characteristics, v dd = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i xtal_in other inputs 0v to v dd -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ? ja 53.5 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 24 ma i ddo output supply current no load 27 ma symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 24 ma i ddo output supply current no load 26 ma symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current 24 ma i ddo output supply current no load 29 ma
rev b 3/25/15 4 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet table 3d. power supply dc characteristics, v dd = v ddo = 2.5v5%, t a = -40c to 85c table 3e. power supply dc characteristics, v dd = 2.5v5%, v ddo = 1.8v0.2v, t a = -40c to 85c table 3f. lvcmos/lvttl dc characteristics, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information section. load test circuit diagrams. table 4. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 23 ma i ddo output supply current no load 25 ma symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current 23 ma i ddo output supply current no load 24 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current clk_sel, lvcmos_clk v dd = v in = 3.465v 150 a i il input low current clk_sel, lvcmos_clk v dd = 3.465v, v in = 0v -5 a v oh output high voltage v ddo = 3.465v 2.6 v v ddo = 2.625v 1.8 v v ddo = 2v v ddo ? 0.3 v v ol output low voltage v ddo = 3.465 or 2.625v 0.5 v v ddo = 2v 0.35 v parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 10 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
low skew, 1:18 crystal-to-lvcmos/lvttl fanout buffer 5 rev b 3/25/15 83918 data sheet ac electrical characteristics table 5a. ac characteristics, v dd = v ddo = 3.3v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at f out unless noted otherwise. note 1: measured from v dd /2 of the input to v ddo /2 of the output. note 2: refer to the phase noise plot following this section. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same tem perature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units f out output frequency 200 mhz tp lh propagation delay, low to high; note 1 1.85 3.0 ns t jit(?) rms phase jitter, (random); note 2 25mhz, integration range: 1khz to 1mhz 0.449 ps t jit additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz to 20mhz 0.145 ps t sk(o) output skew; note 3, 6 75 ps t sk(pp) part-to-part skew; note 4, 6 800 ps t r / t f output rise/fall time; note 5 20% to 80% 300 700 ps odc output duty cycle ? out ? 150mhz 45 55 %
rev b 3/25/15 6 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet table 5b. ac characteristics, v dd = 3.3v5%,v ddo = 2.5v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at f out unless noted otherwise. note 1: measured from v dd /2 of the input to v ddo /2 of the output. note 2: refer to the phase noise plot following this section. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same tem perature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. table 5c. ac characteristics, v dd = 3.3v5%,v ddo = 1.8v0.2v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at f out unless noted otherwise. note 1: measured from v dd /2 of the input to v ddo /2 of the output. note 2: refer to the phase noise plot following this section. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same tem perature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f out output frequency 200 mhz tp lh propagation delay, low to high; note 1 23ns t jit(?) rms phase jitter, (random); note 2 25mhz, integration range: 1khz to 1mhz 0.465 ps t jit additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz to 20mhz 0.161 ps t sk(o) output skew; note 3, 6 75 ps t sk(pp) part-to-part skew; note 4, 6 1ns t r / t f output rise/fall time; note 5 20% to 80% 300 700 ps odc output duty cycle ? out ? 150mhz 45 55 % symbol parameter test conditio ns minimum typical maximum units f out output frequency 200 mhz tp lh propagation delay, low to high; note 1 1.65 4.3 ns t jit(?) rms phase jitter, (random); note 2 25mhz, integration range: 1khz to 1mhz 0.595 ps t jit additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz to 20mhz 0.228 ps t sk(o) output skew; note 3, 6 75 ps t sk(pp) part-to-part skew; note 4, 6 1ns t r / t f output rise/fall time; note 5 20% to 80% 200 800 ps odc output duty cycle ? out ? 150mhz 40 60 %
low skew, 1:18 crystal-to-lvcmos/lvttl fanout buffer 7 rev b 3/25/15 83918 data sheet table 5d. ac characteristics, v dd = v ddo = 2.5v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambi ent operating temperature range, which is established when th e device is mounted in a test socket with maintained trans verse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at f out unless noted otherwise. note 1: measured from v dd /2 of the input to v ddo /2 of the output. note 2: refer to the phase noise plot following this section. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as the skew between outputs on different device s operating at the same supply voltage, same frequency, same tem perature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. table 5e. ac characteristics, v dd = 2.5v5%,v ddo = 1.8v0.2v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambi ent operating temperature range, which is established when th e device is mounted in a test socket with maintained trans verse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured at f out unless noted otherwise. note 1: measured from v dd /2 of the input to v ddo /2 of the output. note 2: refer to the phase noise plot following this section. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as the skew between outputs on different device s operating at the same supply voltage, same frequency, same tem perature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units f out output frequency 200 mhz tp lh propagation delay, low to high; note 1 23ns t jit(?) rms phase jitter, (random); note 2 25mhz, integration range: 1khz to 1mhz 0.478 ps t jit additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz to 20mhz 0.157 ps t sk(o) output skew; note 3, 6 75 ps t sk(pp) part-to-part skew; note 4, 6 1ns t r / t f output rise/fall time; note 5 20% to 80% 300 700 ps odc output duty cycle ? out ? 150mhz 45 55 % symbol parameter test conditio ns minimum typical maximum units f out output frequency 200 mhz tp lh propagation delay, low to high; note 1 1.75 3.85 ns t jit(?) rms phase jitter, (random); note 2 25mhz, integration range: 1khz to 1mhz 0.591 ps t jit additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz to 20mhz 0.175 ps t sk(o) output skew; note 3, 6 75 ps t sk(pp) part-to-part skew; note 4, 6 1.15 ns t r / t f output rise/fall time; note 5 20% to 80% 200 800 ps odc output duty cycle ? out ? 150mhz 45 55 %
rev b 3/25/15 8 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet typical phase noise at 25mhz cr ystal (3.3v core/3.3v output) noise power dbc hz offset frequency (hz)
low skew, 1:18 crystal-to-lvcmos/lvttl fanout buffer 9 rev b 3/25/15 83918 data sheet additive phase jitter (2.5v output) the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. the source generator "ifr2042 10k hz ? 56.4ghz low noise signal generator as external input to an agilent 8133a 3ghz pulse generator". additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.161ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
rev b 3/25/15 10 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet parameter measureme nt information 3.3 core/3.3v output load ac test circuit 3.3v core/1.8v output load ac test circuit 2.5v/1.8v output load ac test circuit 3.3v core/2.5v output load ac test circuit 2.5v/2.5v output load ac test circuit rms phase jitter scope qx gnd 1.65v5% -1.65v5% v dd, v ddo v dd v ddo scope qx gnd 2.4v5% -0.9v0.1v 0.9v0.1v v dd v ddo scope qx gnd 1.6v0.025v -0.9v0.1v 0.9v0.1v v dd v ddo scope qx gnd 2.05v5% -1.25v5% 1.25v5% v dd v ddo scope qx gnd 1.25v5% -1.25v5% v dd, v ddo
low skew, 1:18 crystal-to-lvcmos/lv ttl fanout buffer 11 rev b 3/25/15 83918 data sheet parameter measurement in formation, continued output skew output rise/fall time output duty cycle/pulse width/period part-to-part skew propagation delay qx qy t sk(b) v cco 2 v cco 2 20% 80% 80% 20% t r t f q0:q17 q0:q17 qx qy t sk(pp) v ddo 2 v ddo 2 part 1 part 2 t pd v dd 2 v ddo 2 q0:q17 lvcmos_clk
rev b 3/25/15 12 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet applications information crystal input interface the 83918 has been characterized with 18pf parallel resonant crystals. the capacitor val ues, c1 and c2, shown in figure 1 below were determined using an 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 1. crystal input interface overdriving the xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 2a. the xtal_out pin can be left floating. the maximum amplitude of the input signal should not exceed 2v and the input edge rate can be as slow as 10ns. this configuration requires that the output impedance of t he driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpec l driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 27pf c2 27pf r2 100 r1 100 rs 43 ro ~ 7 ohm driv er_lvcmos zo = 50 ohm c1 0.1uf 3.3v 3.3v cry stal input interf ace xta l _ i n xta l _ o u t cry stal input interf ace xtal_in xtal_out r3 50 c1 0.1uf r2 50 r1 50 zo = 50 ohm lvpecl zo = 50 ohm vcc=3.3v
low skew, 1:18 crystal-to-lvcmos/lv ttl fanout buffer 13 rev b 3/25/15 83918 data sheet recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. lvcmos_clk input for applications not requiring the us e of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the lvcmos_clk to ground. lvcmos control pin the control pin has an internal pulldown; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos outputs can be left floating. we recommend that there is no trace attached.
rev b 3/25/15 14 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 83918. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 83918 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd + i ddo ) = 3.465v *(24ma + 27ma) = 176.7mw dynamic power dissipation at 200mhz power (200mhz) = c pd * frequency * (v dd ) 2 * number of outputs = 9pf * 200mhz * (3.465v) 2 * 18 = 389mw total power dissipation ? total power = power (core) max + power (200mhz) = 176.7mw + 389mw = 565.7mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 53.5c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.566w * 53.5c/w = 115.3c. th is is well below the limit of 125c. this calculation is only an example. tj will vary depending on the number of loaded outputs, supply voltage, air flow and the t ype of board (multi-layer). table 6. thermal resistance ? ja for 32 lead lqfp, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 53.5c/w 48.0c/w 44.0c/w
low skew, 1:18 crystal-to-lvcmos/lv ttl fanout buffer 15 rev b 3/25/15 83918 data sheet reliability information table 7. ? ja vs. air flow table for a 32 lead lqfp transistor count the transistor count for 83918 is: 909 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 53.5c/w 48.0c/w 44.0c/w
rev b 3/25/15 16 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet package outline and package dimensions package outline - y suffix for 32 lead lqfp table 8. package dimensions for 32 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: bbc - hd all dimensions in millimeters symbol minimum nominal maximum n 32 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.60 ref. e 0.80 basic l 0.45 0.60 0.75 ? 0 7 ccc 0.10
low skew, 1:18 crystal-to-lvcmos/lv ttl fanout buffer 17 rev b 3/25/15 83918 data sheet ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 83918ayilf ics83918ayil ?lead-free? 32 lead lqfp tray -40 ? c to 85 ? c 83918ayilft ics83918ayil ?lead-free? 32 lead lqfp tape & reel -40 ? c to 85 ? c
rev b 3/25/15 18 low skew, 1:18 cryst al-to-lvcmos/lvttl fanout buffer 83918 data sheet revision history sheet rev table page description of change date b t5a, t5b, t5d, t5e t5d 5 - 7 7 ac characteristic tables - added test conditions to output duty cycle. 2.5 ac characteristics table - changed part-to-part skew from 1.1ns max to 1.0 ns max. 8/17/10 b t9 17 ordering information - removed leaded devices. updated data sheet format. 3/25/15
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